Welcome to IEEE TCCA Email-Monthly, Jan. 2003: 1. HPCA-9: The International Symposium on High-Performance=20 Computer Architecture submitted by: Soner Onder CALL FOR PARTICIPATION http://www.cs.arizona.edu/hpca9 =20 2. PacRim'03: The 2003 IEEE Pacific Rim Conference on Communications,=20 Computers and Signal Processing submitted by: Kin F. Li =20 Call for Paper http://www.PacRimConf.ca 3. 1st Workshop on Optimizations for DSP and Embedded Systems (ODES) held in conjunction with CGO (Int. Sym. on Code Generation=20 and Optimization) Submitted by Chris Newburn 4. ASAP 2003: 14th IEEE International Conference on Application-specific Systems, Architectures and Processors =20 submitted by: Mainak Sen Call for Paper http://www.ece.rice.edu/asap2003/ 5. ICS 2003: 17th International Conference on Supercomputing submitted by: Michael Gschwind =20 CALL FOR PAPERS http://www.csit.fsu.edu/ics03 * Archive: http://www.ele.uri.edu/tcca * To submit an email message to be distributed among TCCA members,=20 send an email to qyang@ele.uri.edu * To subscribe to this mailing list, please sign up at * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe=20 ----------------------------------------------------------------------- Qing (Ken) Yang, Professor =09 Distinguished Engineering Professor e-mail: qyang@ele.uri.edu =20 Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 =20 University of Rhode Island Fax (401) 782-6422 =20 Kingston RI. 02881 http://www.ele.uri.edu/~qyang = =20 ------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ *--------------------------------------------------------------------* * CALL FOR PARTICIPATION *=20 * * * ON-LINE REGISTRATION is now OPEN. * * EARLY REGISTRATION DEADLINE: * * 5:00pm Eastern FRIDAY, JANUARY 17, 2003. * * * * Please note: * * Early registration deadline is 8 days away. * * In order to get the conference rate, hotel reservations * * must be made by Jan 17. * * * * NP-2 Workshop has been extended to 1-1/2 days now. * * Network processors tutorial date/time/organizers change. * *--------------------------------------------------------------------* =20 HPCA - 9 =20 =20 Anaheim, California =20 February 8-12, 2003 =20 =20 The International Symposium on High-Performance Computer Architecture=20 provides a high quality forum for scientists and engineers to present=20 their latest research findings in this rapidly changing field. HPCA-9,=20 the ninth in the series of International Symposium on High Performance=20 Computer Architecture, will be held in Anaheim, California. =20 Please visit the conference web page at: =20 http://www.cs.arizona.edu/hpca9 =20 =20 =20 *****=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D***** * ADVANCE PROGRAM * *****=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D***** =20 *=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D* * Saturday, February 8 * *=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D* Workshops (8:00am - 5:00pm) --------------------------- INTERACT-7 =20 The 7th Annual Workshop on Interaction between Compilers and=20 Computer Architecture =20 SAN-2 =20 2nd Annual Workshop on Novel Uses of System Area Networks =20 NP-2 =20 The Second Workshop on Network Processors =20 (Starts 1:30pm) =20 Tutorial (8:30am - 12:30n) --------------------------- An introduction to Network Processors =20 Patrick Crowley, U. Washington =20 Raj Yavatkar, Intel Corporation =20 *=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D* * Sunday, February 9 * *=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D* Workshops (8:00am - 5:00pm) --------------------------- CAECW =20 Sixth Workshop on Computer Architecture =20 Evaluation using Commercial Workloads =20 =20 NP-2 =20 The Second Workshop on Network Processors =20 =20 SSRS =20 Workshop on Software Support for Reconfigurable =20 Systems =20 =20 Tutorial (Morning) -------------------- New Computing Platforms for Embedded Systems =20 Frank Vahid & Walid Najjar, U. California Riverside =20 =20 Tutorial (Afternoon) -------------------- Simics Microarchitect's Toolset =20 Peter Magnuson, Virtutech =20 *=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D* * Monday, February 10 * *=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D* ---------------------------------------------------------------------- Welcome (8:45am - 9:00am) =20 ---------------------------------------------------------------------- ---------------------------------------------------------------------- Keynote I (9:00am - 10:00am) Chair : Laxmi Bhuyan ---------------------------------------------------------------------- Billion Transistor Chips in Mainstream Enterprise Platforms of=20 the Future Dileep Bhandarkar Architect-at-large, Enterprise Platforms Group, Intel Corporation ---------------------------------------------------------------------- ---------------------------------------------------------------------- Break (10:00 am - 10:30 am) ---------------------------------------------------------------------- ---------------------------------------------------------------------- Session 1 : Multithreading (10:30am -- 12:00n) Chair: Antonio Gonzalez Variability in Architectural Simulations of Multi-threaded=20 Workloads Alaa Alameldeen and David Wood Mini-threads: Increasing TLP on Small-Scale SMT Processors Joshua Redstone, Susan Eggers, and Henry Levy Front-End Policies for Improved Issue Efficiency in SMT=20 Processors Ali El-Moursy and David Albonesi ---------------------------------------------------------------------- ---------------------------------------------------------------------- Lunch (12:00n - 1:30pm) ---------------------------------------------------------------------- ---------------------------------------------------------------------- Session 2 : Branch Prediction (1:30pm - 3:00pm) Chair: Susan Eggers Reconsidering Complex Branch Predictors Daniel Jimenez Incorporating Predicate Information Into Branch Predictors Beth Simon, Brad Calder, and Jeanne Ferrante Dynamic Data Dependence Tracking and its Application to Branch=20 Prediction Lei Chen, Steve Dropsho, and David Albonesi ---------------------------------------------------------------------- ---------------------------------------------------------------------- Break (3:00pm - 3:30 pm) ---------------------------------------------------------------------- ---------------------------------------------------------------------- Session 3 : Power Efficient Designs (3:30pm - 5:30pm) Chair: Saman Amarasinghe Control Techniques to Eliminate Voltage Emergencies in=20 High-Performance Processors Russ Joseph, David Brooks, and Margaret Martonosi Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks Li Shang, Li-Shiuan Peh, and Niraj Jha Power-Aware Control Speculation through Selective Throttling Juan L. Aragon, Jose Gonzalez, and Antonio Gonzalez Deterministic Clock Gating For Microprocessor Power Reduction Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, and=20 T.N. Vijaykumar ---------------------------------------------------------------------- ---------------------------------------------------------------------- BANQUET ---------------------------------------------------------------------- *=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D* * Tuesday, February 11 * *=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D* ---------------------------------------------------------------------- Keynote II (8:30am - 9:30am) Chair: Brad Calder Beyond Performance: Some (other) Challenges for Future=20 Microprocessors. Eric Kronstadt Director, VLSI Systems, IBM TJ Watson ---------------------------------------------------------------------- ---------------------------------------------------------------------- Break (9:30am - 10:00am) ---------------------------------------------------------------------- ---------------------------------------------------------------------- Session 4 : Superscalars (10:00am - 12:00n) Chair: David Wood Runahead Execution: An Alternative to Very Large Instruction=20 Windows for Out-of-order Processors Onur Mutlu, Jared Stark, Chris Wilkerson, and Yale Patt Microarchitecture and Performance Analysis of a SPARC-V9=20 Microprocessor for Enterprise Server Systems Mariko Sakamoto, Akira Katsuno, Alichiro Inoue, Takeo Asakawa, Haruhiko Ueno, and Kuniki Morita Exploring the VLSI Scalability of Stream Processors Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, John Owens, and Brain Towles Dynamic Optimization Of Micro-Operations Brian Slechta, Brian Fahs, David Crowe, Michael Fertig, Gregory Muthler, Justin Quek Francesco Spadini, Sanjay J. Patel, and Steven S. Lumetta ---------------------------------------------------------------------- ---------------------------------------------------------------------- Luncheon (12:00n - 1:30pm) ---------------------------------------------------------------------- ---------------------------------------------------------------------- Session 5 : Multiprocessor Systems (1:30pm - 3:00pm) Chair: Chita Das Slipstream Execution Mode for CMP-Based Multiprocessors Khaled Ibrahim, Gregory Byrd, and Eric Rotenberg Tradeoffs in Buffering Memory State for Thread-Level Speculation=20 in Multiprocessors Maria Garzaran, Milos Prvulovic, Victor Vinals, Jose Llaberia, Lawrence Rauchwerger, and Josep Torrellas Dynamic Data Replication: An approach to Providing Fault-Tolerant=20 Shared Memory Clusters Rosalia Christodoulopoulou, Reza Azimi, and Angelos Bilas ---------------------------------------------------------------------- ---------------------------------------------------------------------- Break (3:00pm - 3:30pm) ---------------------------------------------------------------------- ---------------------------------------------------------------------- Session 6 : Memory and Communication Performance (3:30pm - 5:30pm) Chair: David Albonesi Memory System Behavior of Java-Based Middleware Martin Karlsson, Kevin Moore, Erik Hagersten, and David Wood Evaluating the Impact of Communication Architecture on the Performability of Cluster-Based Services Kiran Nagaraja, Neeraj Krishnan, Ricardo Bianchini, Richard Martin, and Thu Nguyen Hierarchical Back-Off Lock for Non-Uniform Communication=20 Architectures Zoran Radovic and Erik Hagersten Performance Enhancement Techniques for InfiniBand Architecture Eun Jung Kim, Ki Hwan Yum, Chita Das, Mazin Yousif, and Jose Duato ---------------------------------------------------------------------- *=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D* * Wednesday, February 12 * *=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D* ---------------------------------------------------------------------- Keynote III (8:00am - 9:00am) Chair: Josep Torrellas The State of State Peter Kogge McCourtney Professor of Computer Science and Engineering, University of Notre Dame ---------------------------------------------------------------------- ---------------------------------------------------------------------- Session 7 : Profiling and Simulation Support (9:00am - 10:00am) Chair: Bill Mangione-Smith Catching Accurate Profiles in Hardware Satish Narayanasamy, Timothy Sherwood, Suleyman Sair, Brad Calder, and George Varghese A Statistically Rigorous Approach for Improving Simulation=20 Methodology Joshua Yi, David Lilja, and Douglas Hawkins ---------------------------------------------------------------------- ---------------------------------------------------------------------- Break (10:00am - 10:30am) ---------------------------------------------------------------------- ---------------------------------------------------------------------- Session 8 (10:30 am - 12:30 pm) 8A - Caching and Prefetching=20 ---------------------------- Chair: Soner Onder Caches and Merkle Trees for Efficient Memory Authentication Blaise Gassend, Ed Suh, Dwaine Clarke, Marten van Dijk, and Srinivas Devadas =20 Just Say No: Benefits of Early Cache Miss Determination Gokhan Memik, Glenn Reinman, and William Mangione-Smith =20 TCP: Tag Correlating Prefetchers Zhigang Hu, Stefanos Kaxiras, and Margaret Martonosi =20 Cost-sensitive Cache Replacement Algorithms Jaeheon Jeong and Michel Dubois =20 8B - Networks and Communication=20 ------------------------------- Chair: Qing Yang Scalar Operand Networks Michael Taylor, Walter Lee, Saman Amarasinghe, and=20 Anant Agarwal Inter-cluster Communication Models for Clustered VLIW processors Andrei Terechko, Erwan Le Thenaff, Manish Garg, Jos van Eijndhoven, and Henk Corporaal A Methodology for Designing Efficient On-Chip Interconnects on Well-behaved Communication Patterns Wai Hong Ho and Timothy Pinkston Active I/O Switches in System Area Networks Ming Hao and Mark Heinrich *****=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D***** * End of program * *****=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D***** PacRim'03: The 2003 IEEE Pacific Rim Conference on Communications,=20 Computers and Signal Processing submitted by: Kin F. Li Call for Papers and Special Sessions: http://www.PacRimConf.ca ---------------------------------------------------------------------- CALL FOR PAPERS =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D 1st Workshop on Optimizations for DSP and Embedded Systems (ODES) held in conjunction with CGO (Int. Sym. on Code Generation and Optimization) March 23, 2003, San Francisco, CA, USA SUBMISSION DEADLINE: JANUARY 17, 2003 The performance requirements of digital signal processing and embedded applications are rapidly increasing, but the power and cost budgets are decreasing. Optimization plays a very important role in managing the conflicting demands. The focus of this workshop is to understand the various optimization strategies applicable to the design of DSP and embedded systems for performance, power, and cost. TOPICS OF INTEREST ------------------ Topics of interest include, but are not limited to: * Algorithmic transformations and code/software optimizations * Hardware and software optimizations for low-power consumption and/or code density * Coprocessor and hardware accelerators * Compiler techniques and code generation for media processing * Frameworks for profiling and scheduling tasks (multiple/ concurrent) on various hardware resources (single-core + hardware accelerators, dual-core, system-on-a-chip, etc) * Hardware/software tradeoffs with ASICs, FPGA's, DSPs, general-purpose processors, microcontrollers, etc as building blocks * Retargetable compilers and reconfigurable architectures IMPORTANT DATES AND DEADLINES ----------------------------- Submission: January 17, 2003 Acceptance: February 14, 2003 Final version: March 7, 2003 SUBMISSION GUIDELINES --------------------- To encourage participation, we are not asking for full papers for this first workshop. Please submit an extended abstract, and a corresponding foil set. Clearly describe the nature of the work, its significance and the current status of the research. Include the list of authors and their affiliations, addresses, telephone and fax numbers, email addresses and the name of the corresponding author. A web site will be available for electronic submission shortly. Watch for an updated call for papers. In the mean time, please submit extended abstracts to: Deepu Talla Texas Instruments 12500 TI Blvd, M/S 8638 Dallas, TX 75243 deepu@ti.com OR Lizy K. John ECE Department 1 University Station, C0803 The University of Texas Austin, TX 78712 ljohn@ece.utexas.edu PROGRAM COMMITTEE ----------------- Shuvra Bhattacharyya University of Maryland Steve Carr Michigan Technological University Pradeep Dubey Broadcom Jose Fridman Analog Devices Jason Fritts University of Washington at St. Louis Tor Jeremiassen Texas Instruments Eugene John University of Texas at San Antonio Lizy John University of Texas at Austin Vinod Kathail Hewlett Packard Rainer Leupers Aachen University of Technology Vijay Madisetti Georgia Tech John Reekie University of California at Berkeley Deepu Talla Texas Instruments -------------------------------------------------------------------------= - +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++ ASAP 2003 CALL FOR PAPERS +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++ 14th IEEE International Conference on Application-specific Systems, Architectures and Processors The Hague, The Netherlands, June 24-26, 2003 http://www.ece.rice.edu/asap2003/ Key dates: February 15, 2003: Deadline for submission of papers March 15, 2003: Acceptance notification April 6, 2003: Camera-ready papers due The conference will cover the theory and practice of application-specific systems, architectures and processors. Areas for application-specific com= puting are many and varied. Some sample areas include information systems, signa= l and image processing, multimedia systems, high-speed networks, compression, graphics, and cryptography.=20 Aspects of application-specific computing that are of interest include, b= ut are not limited to:=20 Application-specific systems: network computing, special-purpose systems, performance evaluation, design languages, compilers, operating systems, nanocomputing systems and applications, hardware/software integration, rapid-prototyping.=20 Application-specific architectures: special-purpose designs, design methodology, CAD tools, fault tolerance, specifications and interfaces, networks-on-a-chip, hardware/software codesign, processor arrays,=20 SoC, superscalar, multithreaded, VLIW, and EPIC architectures.=20 Application-specific processors: digital signal processing, computer arithmetic, configurable/custom computing, implementation methodologies, = new technologies, fine-grain parallelism, low-power designs, asynchronous har= dware.=20 The conference will feature a keynote speech, paper presentations, and recreational activities. The proceedings will be published by IEEE Comput= er Society Press. Conference Organizers ----------------------------=20 General Chairs:=20 Ed Deprettere, Leiden University Shuvra Bhattacharyya, University of Maryland =20 Program Chairs:=20 Lothar Thiele, Swiss Federal Institute of Technology Zuerich (Systems= ) Alain Darte, Ecole Normale Superieure de Lyon (Architectures) Joseph Cavallaro, Rice University (Processors)=20 Steering Committee: Jose Fortes, University of Florida=20 S-Y Kung, Princeton University Michael Schulte, University of Wisconsin Earl Swartzlander, University of Texas Program Committee: Shail Aditya, HP Labs Mark Arnold, Lehigh University Magdy Bayoumi, University of Louisiana at Lafayette Neil Burgess, Cardiff University Peter Cappello, University of California at Santa Barbara=20 Liang-Gee Chen, National Taiwan University Gerhard Fettweis, Dresden University of Technology Jose Fortes, University of Florida=20 Guang Gao, University of Delaware=20 Graham Jullien, University of Calgary Israel Koren, University of Massachusetts at Amherst S-Y Kung, Princeton University Tomas Lang, University of California at Irvine Ruby Lee, Princeton University Wayne Luk, Imperial College Elias Manolakos, Northeastern University=20 John McCanny, Queen's University of Belfast Jean-Michel Muller, Ecole Normale Sup. de Lyon Praveen Murthy, Fujitsu Laboratories of America=20 Tobias Noll, Aachen Institute of Technology Keshab Parhi, University of Minnesota at Twin Cities=20 Peter Pirsch, University of Hannover Gang Qu, University of Maryland Patrice Quinton, IRISA, Campus de Beaulieu Sanjay Rajopadhye, Colorado State University=20 Michael Schulte, University of Wisconsin-Madison Earl Swartzlander, University of Texas at Austin Juergen Teich, Paderborn University Mateo Valero, Technical University of Catalonia=20 Pieter van der Wolf, Philips Research Laboratories Stamatis Vassiliadis, Delft University of Technology Ingrid Verbauwhede, University of California at Los Angeles Doran Wilde, Brigham Young University=20 Roger Woods, Queen's University of Belfast Kung Yao, University of California at Los Angeles Pen-Chung Yew, University of Minnesota at Twin Cities -------------------------------------------------------------------------= - The ICS 2003 Paper Submission Deadline is ONE MONTH AWAY. =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D CALL FOR PAPERS ICS '03 17th International Conference on Supercomputing=20 June 23-26, 2003=20 San Francisco Bay Area=20 USA =20 Sponsored by ACM/SIGARCH =20 =20 ICS is the premier international forum for the presentation of research results in high-performance computing systems. Now in its 17th year, the conference also includes invited talks, tutorials, workshops, panels, and exhibits. The San Francisco Bay Area - the most sought after tourist destination in the entire world and the home of Silicon Valley - will host the conference in 2003. Papers are solicited on all aspects of research, development, and application of high-performance systems, including new experimental and commercial systems, architectures with fine and coarse grain parallelism, grid computing, novel infrastructures for the Internet, parallel I/O and storage, embedded and power-aware computer architectures, operating systems and support software, restructuring and optimizing compilers, program development tools, high-performance Java, performance evaluation studies, numerical or non-numerical algorithms, and computationally challenging scientific applications. Papers should not exceed 6,000 words, and must be submitted electronically using the submission form available at http://www.csit.fsu.edu/ics03. Submissions must be in PDF or postscript format. Workshop and tutorial proposals are solicited, and are due by March 17, 2003. For further information and future updates, refer to the ICS'03 web site at http://www.csit.fsu.edu/ics03, or contact the General or Program Chairs. GENERAL CHAIR Dr. Utpal Banerjee Intel Corporation Santa Clara, CA=20 utpal.banerjee@intel.com =20 PROGRAM CO-CHAIRS Prof. Kyle A. Gallivan=20 Florida State University=20 Tallahassee, FL=20 gallivan@csit.fsu.edu=20 Prof. Antonio Gonz=E1lez Intel Labs & Univ. Polit=E8cnica de Catalunya=20 Barcelona, Spain=20 antoniox.gonzalez@intel.com =20 IMPORTANT DATES Paper submission deadline: February 10, 2003 =20 Author notification: April 7, 2003=20 Final papers due: May 7, 2003 =20 =20 ------=20 Thank you very much for your time in reading this announcement. If you have any questions about ICS '03, please contact me at mikeg@watson.ibm.c= om,=20 and I would be happy to help to the extent I can. Please feel free to pass this announcement on to other colleagues who might be interested. We hope you will enjoy the ICS '03 Web site. Dr. Michael Gschwind -------------------------------------------------------------------------= - * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe=20